The present invention relates generally to integrated circuit (IC) fabrication. More particularly, the present invention relates to a system for and a method of cleaning a top surface of an IC substrate.
SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from, the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.
Conventional processes pre-clean the top surface of the wafer to remove oxide before metal deposition. For example, when gate conductors and source and drain regions are silicided, a cleaning process (e.g., a plasma PCII clean process) can provide a biased plasma of argon to physically sputter and pre-clean the wafer surface. The pre-cleaning can be performed to reduce the amount of native oxides (e.g., thin silicon dioxide (SiO2) layers) on the top surface of the wafer and the gate conductor. Native oxides prevent an appropriate silicidation reaction in subsequent steps.
After pre-cleaning, a metal layer can be deposited over the top surface of the wafer and the gate conductor. The metal layer can be reacted with the semiconductor surface of the wafer and the gate conductor to form metal silicide (MexSiy) regions. Metal silicide regions can include layers of titanium silicide, nickel silicide, cobalt silicide, etc.
Heretofore, conventional pre-cleaning processes have used a purely physical plasma pre-cleaning process such as the plasma PCII clean process. Purely physical plasma pre-cleaning processes have caused germanium resputtering from the wafer surface. Germanium resputtering can also occur from the gate conductor if a silicon germanium or strained silicon gate conductor is used. Germanium resputtering can contaminate the walls of the chamber of the fabrication equipment. In addition, argon pre-cleaning processes can unnecessarily consume silicon and cause silicon damage.
Germanium contamination of IC equipment is becoming a more serious issue as IC fabrication processes explore the advantages of the higher carrier mobility of strained silicon (SMOS) devices. IC fabrication equipment that tends to become contaminated with germanium can include deposition chambers, furnaces, diffusion equipment, etching tools, etc. The quartzware associated with such equipment is particularly susceptible to germanium contamination.
Germanium contamination is particularly problematic when equipment is used in both non-germanium and germanium fabrication lines. Shared equipment must be purged of germanium contamination before it is used in non-germanium processes, because such contamination is particularly damaging to metals used during conventional IC fabrication. Further, high levels of germanium contamination can be problematic even for strained silicon (SMOS) processes.
Flash devices are particularly sensitive to low level germanium contamination, because Flash technology uses IC structures and processes that are incompatible with germanium. For example, germanium contamination may cause data retention problems for the Flash memory cell. It is nevertheless desirous to use equipment associated with the Flash fabrication line with germanium containing products (e.g., SMOS products).
Thus, there is a need for an efficient process for pre-cleaning a wafer surface and a gate conductor. Further, there is a need for a system and a method which reduces germanium contamination caused by conventional pre-cleaning. Even further, there is a need for a method of reducing germanium contamination from a strained silicon layer. Yet further, there is a need for a process which reduces the adverse effects of germanium on silicidation processes. Further, there is a need for a pre-cleaning process that allows shared equipment to be used in both a Flash production line and a germanium production line.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a substrate, providing a gate structure above the substrate and pre-cleaning the substrate with an argon and hydrogen plasma. The substrate includes a layer including germanium. The method also includes siliciding the substrate.
Another exemplary embodiment relates to a method of pre-cleaning a top surface of an IC substrate before silicidation in a chamber. The method includes providing a plasma including hydrogen in the chamber and removing native oxide from the IC substrate. In one embodiment, a wet bath can be utilized to reduce the thickness of the native oxide layer before the providing step.
Yet another exemplary embodiment relates to a method of manufacturing a transistor on an integrated circuit. The method includes providing a gate structure on a top surface of a strained silicon layer or a silicon germanium layer, providing a plasma including hydrogen and argon to remove a native oxide material, and siliciding the top surface.